1. Field of the Invention
The present invention relates to a placement configuration of an electrostatic capacitance element having a metal—insulation film—metal (MIM) structure, more particularly to a placement configuration of two MIM type capacitance elements having an identical capacitance value.
2. Description of the Related Art
An analog integrated circuit used in a mobile communication device such as a cellular telephone is provided with passive elements such as a capacitance element, a resistance and an inductor. As the capacitance element among the passive elements, which is particularly frequently used in an operational amplifier of a pipeline-type A/D converter, two capacitance elements having an identical capacitance value are used in order to eliminate any error generated in the A/D conversion, and a high relative precision is demanded between the two capacitance elements. The relative precision refers to a differential between capacitance values of the two capacitance elements that are identically structured (ΔC=2×(C1−C2)/(C1+C2)).
Examples of the capacitance element conventionally used in the integrated circuit include an MOS type capacitance element in which a thin oxide silicon (SiO2) film or the like is sandwiched between an electrode such as a metallic film or a conductive polycrystal silicon (poly-Si) film and a silicon (Si) substrate, a two-layered poly-Si type capacitance element in which a thin SiO2 layer or the like is sandwiched between two-layer conductive poly-Si, and the like. These capacitance elements have the following problems. One of the problems is that there is a large parasitic resistance because an impurity diffusive layer or a conductive poly-Si film in a supported substrate is used in one or both of the electrodes. The next problem is that a parasitic capacitance is increased because a distance by which the electrode and Si substrate are isolated from each other is approximately not more than a thickness of an insulation film for isolating the elements. Further, because a depletion layer in the Si substrate changes in response to an applied voltage, a value of the parasitic capacitance fails to remain constant with respect to the voltage.
In order to deal with the foregoing problems, an MIM (Metal Insulator Metal) type capacitance element, an example of which is recited in No. 2001-203329 of the Publication of the Unexamined Japanese Patent Applications, has been gathering attention. According to the cited document, metal films having a low resistance constitute upper and lower electrodes, and an upper-layer wiring is used as the electrodes so that the electrodes can be formed with an appropriate distance from the Si substrate. As a result, the parasitic resistance and the parasitic capacitance can be significantly reduced.
However, in the conventional constitution described above, if the two MIM type capacitance elements having the identical capacitance value are not carefully placed, the obtained relative precision is not as high as expected due to a variation generated in the capacitance insulation film when the film is formed, a variation generated in processing the capacitance electrode, and an influence of a parasitic capacitance from a peripheral circuit element.
The present invention aims to solve the foregoing problems, and a main object thereof is to regulate the placement of the two MIM type capacitance elements having the identical capacitance value to thereby realize such a placement configuration of the MIM type capacitance elements that a high relative precision can be obtained.